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FPGA Design Services and Check

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Design Services

Our FPGA design services leverage a world-class team of design experts to expedite your design cycle with guaranteed quality. We tailor our expert services to key vertical and horizontal solutions for Machine Learning (ML), Smart Embedded Vision (SEV), high-speed communications and motor control. Design offerings include a broad range of design items such as new module and IP development, IP customization, design optimization, fitting and system development.

Leverage our:      

  • FPGA/SoC experts: a team of experts with experience with our FPGAs and popular industry-standard development tools.
  • Proven design capabilities: extensive application experience with FPGA/SoC model-based designs, HDL IP and firmware development.
  • Guaranteed quality and reliability: certified quality management process.
  • Robust risk management process: structured, transparent and continually reassessed process with a dedicated program manager

Our Solutions

Reduce Risks and Costs and Fast-Track Your FPGA Design in Three Easy Steps

  1. Talk to us to help us understand your design requirements. 
  2. Work with us to craft and sign a Statement of Work (SoW).
  3. Perform periodic reviews as we develop and test your design.
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Learn More About FPGA Design Services

Design Check

We also offer FPGA design check services that support your product cycle by providing comprehensive review feedback for your Microchip FPGA-based design. Our in-house team of design experts will examine your design schematic and PCB layout to check for DDR and SerDes signal integrity and power integrity. We also provide a consolidated report containing observations, personalized feedback and optimization recommendations. Please see the table below to learn more about the full range of services our design check program offers.

Description Charges and Turnaround Time Items Covered and Delivery Format Requirements From the Client
FPGA Design Check L1 Free
  • N/A
FPGA Design Check L2: Schematics Only $3,000
Turnaround: 5 days
  • Document with observations and recommendations for:
    • Quick check of board design guidelines
    • Libero® SoC Design Suite PDC checks for interface use
    • I/O assignment based on usage
    • SerDes lane assignments, SerDes clocking schemes
    • Programming scheme use cases
    • Reset and clocking scheme
    • Power delivery to FPGA only, decoupling recommendations
  • Schematics
FPGA Design Check L3: Signal Integrity and Power Integrity

DDR:
$5,000
Turnaround: 8 days
  • Document report with standard simulation results
  • Schematics
  • Layout file (preferred format is Allegro .brd file)
  • Board stack-up with all necessary details
  • Additional questions, if any (discussed)

SerDes:
$6,000
Turnaround: 10 days
  • Document report with setup details, modeling and cutout recommendations
Power Integrity Simulation and Optimization:
$12,000
Turnaround: 20 days
  • Document report with simulation results
  • Document report with optimization recommendations
FPGA Design Check L4: Bundle Service (Includes L2 and L3 Services) $22,000
(Price reflects 15% discount on total cost of L2 and L3 services if purchased separately)
  • All the above
  • All the above
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