There are several versions of the CAN bus specification:

• 2.0A – 11 bit message identifier (Standard ID)
• 2.0B – 29 bit message identifier (Extended ID)
• 2.0B Passive – ignores 29-bit message identifier
• 2.0B Active – handles both 11-bit and 29-bit identifier
• CAN FD – backwards compatibility with CAN 2.0B with support for bit rates greater than 1 Mbps and payloads greater than 8 Bytes/frame

The CAN protocol supports five types of frames which include data frame, remote frame, error frame, overload frame, and interframe space.

In general, there are two functional blocks in a CAN node: 

1. The CAN controller, which is integrated in the MCU
2. The CAN transceiver, which is the physical-level interface 

We offer a wide range of CAN transceivers. The diagram below shows the typical architecture for a CAN network.

CAN FD improves the bandwidth utilization of the CAN bus and protocol. The increase in bandwidth utilization is achieved by:

• Dual bit rate: CAN FD frames support dual-bit-time capability
• Normal Bit Time - The bit time is identical to the existing CAN protocol. This includes those fields where multiple devices can transmit simultaneously, at the arbitration start and acknowledgement end.
• Reduced Bit Time - To achieve higher data rates, CAN FD allows bit times for certain fields that are shorter than the current CAN bit time. Timing requirements for these fields are less stringent as it is guaranteed that the devices only transmit one after another. Bit-wise arbitration is not needed. These fields include two control bits, payload length (4 bits), payload data, and CRC (17 or 21 bits).
• Payload increase:
• The maximum message length is 64 bytes compared to 8 bytes previously, improving the efficiency of the CAN protocol.
• To take advantage of this improvement in CAN FD, you also need to update the system software.

• 40, 50 MHz performance
• Up to 512 KB Flash/64 KB RAM
• Full-Speed OTG
• One CAN 2.0B
• 64/100 pins

• 48 MHz performance
  
• Up to 256 KB Flash/32 KB SRAM
  
• Dual CAN FD
  
• 5V compliant
  
• Peripheral Touch Controller (PTC)
• AEC-Q100 Grade 1 qualification

• 48 MHz performance
• Up to 512 KB Flash/64 KB SRAM 
• Secure boot functionality
• Dual CAN FD
• 5V compliant
• Peripheral Touch Controller (PTC)

• 80 MHz performance
• Up to 512 KB Flash/128 KB RAM
• Up to two CAN 2.0B
• USB 2.0-compliant Full-Speed OTG
• 10/100 Ethernet MAC
• 64/100 pins

• 120 MHz performance
• Up to 1 MB Flash/256 KB RAM
• Up to four CAN 2.0B
• Up to two USB 2.0-compliant Full-Speed OTG
  
• 64/100 pins
• 12-bit ADCs

• 120 MHz performance
• Up to 1 MB Flash/256 KB SRAM
• Dual CAN FD
  
• USB FS 2.0 host/device
• 48/64/100/128 pins
• 10/100 Ethernet MAC with IEEE^® 1588 (SAM E53/SAM E54)

• 120 MHz performance
• Up to 1 MB Flash/128 KB SRAM
• Up to two CAN 2.0B
• USB 2.0 Full-Speed device
• 100/144 pins

• 200 MHz performance
• Dual CAN 2.0B
• AEC-Q100
• Up to 2 MB Flash/512 KB SRAM
• 64/100/124/144 pins
• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
  
• 10/100 Ethernet
• 12-bit ADC, crypto engine with RNG

• 300 MHz performance
• Up to 2 MB Flash/384 KB SRAM
• Up to two CAN FD
• AEC-Q100 (SAM V70 and SAM V71)
• FS and HS USB 2.0 Host/Device
• 10/100 Ethernet MAC with IEEE^® 1588/Ethernet-AVB (SAM V71 and SAM E70)
  
• 12-bit ADC, crypto engine with TRNG
  
• 64/100/144 pins

• 300 MHz performance
• Up to 8 MB Flash/1MB SRAM
• Up to six CAN FD
• 10/100/1000 Ethernet MAC with IEEE^® 1588/Ethernet AVB
• Up to two Hi-Speed USB 2.0 interfaces
• 4.6875 Msps 12-bit ADC
• Embedded Hardware Security Module (HSM) for PIC32CZ CA90
• 100, 144, 176 and 208 pins